1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory with backing wirings and a manufacturing method thereof.
2. Description of Related Art
As typified by a nonvolatile memory cell having a MONOS structure (Metal-Oxide-Nitride-Oxide-Semiconductor structure), a cell structure of a nonvolatile memory has been known in which a control gate electrode is formed on a sidewall of a word gate electrode. For example, Japanese Laid-Open Patent Application JP2002-353346A (claiming priority to U.S. Provisional Patent Application serial No. 60/278,622) discloses a cell structure of a flash memory having a twin MONOS structure. FIG. 1 is a sectional view showing a structure of the memory cell having the twin MONOS structure in JP2002-353346A. A memory cell 101 includes a source/drain diffusion layer 144, a word gate insulating film 126, a word gate electrode 130, a control gate electrode 132, an ONO (Oxide Nitride Oxide) film 131, a sidewall insulating film 142, silicide layers 149, 150 and an LDD (Lightly Doped Drain) diffusion layer 138.
The source/drain diffusion layer 144 is formed on the surface of a semiconductor substrate 120. The word gate insulating film 126 is formed on a channel region disposed between the source/drain diffusions layers 144. The word gate electrode 130 is formed on the channel region through the word gate insulating film 126. The control gate electrode 132 is formed on each of both side surfaces of the word gate electrode 130 through the ONO film 131. The ONO film 131 is formed between the word gate electrode 130 and the control gate electrode 132, and between the control gate electrode 132 and the channel region. The sidewall insulating film 142 is formed on each of both sides of the word gate electrode 130 so as to cover the control gate electrode 132. The silicide layers 149, 150 are formed on the word gate electrode 130 and the source/drain diffusion layer 144, respectively. The LDD diffusion layer 138 is formed on the channel region immediately below the sidewall insulating film 142.
Memory cells 101a, 101b are placed on an extension of the memory cell 101 and have a memory cell structure. However, the memory cells 101a, 101b are provided on a isolation region 123 in order to have contact between the memory cell 101 and an upper metal wiring. Such contact is provided for the following reason. A resistance of the control gate electrode 132 is high due to a structural factor that the control gate electrode 132 is formed on the side surfaces of the word gate electrode 130 and a material factor that the control gate electrode is made of polysilicon. Therefore, overall wiring resistance needs to be decreased by “backing” with a metal wiring of a low resistance. The memory cell 101a and the memory cell 101b are connected to each other with a connection layer 135 in a state where the adjacent control gate electrodes 132 are not separated from each other at manufacturing. Thus, the control gate electrode 132 is connected to the upper metal wiring (called backing wiring) through the connection layer 135, a silicide layer 151 on the connection layer 135 and a contact 154 on the silicide layer 151. In the memory cell 101a, the word gate electrode 130 is connected to the upper metal wiring (backing wiring) through the silicide layer 149 and a contact 156 on the silicide layer 149.
We have now discovered the facts that will be described below with reference to attached drawings. Although JP2002-353346A does not disclose the manufacturing method in detail, it is considered from technical common sense that the manufacturing method includes a following manufacturing step. FIGS. 2A to 2B are sectional views each showing a part of a manufacturing step of the memory cell having the disclosed twin MONOS structure. In FIGS. 2A to 2B, a left side of an alternate long and short dash line shows a memory cell region 3 of a nonvolatile semiconductor memory. A right side of the alternate long and short dash line shows a backing region 4 of the nonvolatile semiconductor memory 10. Referring to FIG. 2A, in a memory cell region 3 where the memory cell 101 is formed, the word gate insulating film 126 and the word gate electrode 130 are formed on the semiconductor substrate 120. In a backing region 4 where the memory cells 101a, 101b are formed, the word gate insulating film 126 and the word gate electrode 130 are formed on the isolation region 123 of the semiconductor substrate 120. Then, an ONO film 128 and a polysilicon film 129 are formed so as to cover surfaces of the semiconductor substrate 120 and the word gate electrode 130. Next, in the backing region, a hard mask 125 is formed on a lower region of the polysilicon film 129 between the adjacent word gate electrodes 130. Silicon oxide may be used as the hard mask 125.
Referring to FIG. 2B, the polysilicon film 129 is etched back to remove the polysilicon film 129 except for the area in the vicinity of the side surfaces of the word gate electrode 130. The control gate electrode 132 is formed in this manner. At this time, in the backing region, the polysilicon film 129 between the adjacent control gate electrodes 132, which is protected with the hard mask 125 and is not removed, becomes the connection layer 135. Then, using the word gate electrode 130 and the control gate electrode 132 as masks, the ONO film 128 is formed to the ONO film 131 by etching. In this manner, the ONO film 131 is formed between the word gate electrode 130 and the control gate electrode 132, and between the semiconductor substrate 120 and the control gate electrode 132. In the backing region, the ONO film 128 between the adjacent control gate electrodes 132 which is protected with the connection layer 135 and is not removed becomes an ONO film 139. The hard mask 125 is removed by etching of the ONO film 128.
FIG. 3 is an enlarged sectional view of periphery of the control gate electrode 132 in FIG. 2B. When the polysilicon film 129 is etched in the manufacturing step, a kink 160 occurs in the vicinity of an end of the hard mask 125 between the part which becomes the control gate electrode 132 and the part which becomes the connection layer 135. This is due to when the polysilicon film 129 is etched, a boundary between the control gate electrode 132 and the connection layer 135 is insufficiently protected, resulting in the progress of etching. The kink 160 forces connection between the control gate electrode 132 and the connection layer 135 to have a remarkable high resistance or, in the worst case, to be broken. As a result, the function of the backing for reducing overall wiring resistance by connecting the control gate electrode 132 to the metal wiring cannot be achieved.
By making the thickness of the hard mask 125 relatively large, the occurrence of the kink 160 can be prevented. However, even after etching of the ONO film 128, the thick hard mask 125 still remains. When only a small amount of the hard mask 125 remains, the slicide can not be formed on the connection layer 135 in a subsequent step. As a result, unless the hard mask 125 is completely removed in an additional special step, the resistance between the connection layer 135 and the contact 154 increases. Therefore, there is a demand for the technique capable of preventing the kink from occurring between the control gate electrode and the polysilicon film extended between the control gate electrodes and forming the satisfactory backing wiring structure.